高性能multi-bit delta-sigma音频ADC
100分贝的信噪比
-85 dB THD+N
3个Vpp模拟输入
24位,8至200 kHz采样频率
I2S/LJ主或从模式数据接口
256/384Fs和其他非标准音频系统时钟
低功耗待机模式
Soundbar
音频接口
数字电视
A / V接收器
DVR
NVR
PIN NAME | PIN NUMBER | I/O | DESCRIPTION |
M0, M1 | 15,14 | I | Mode selection |
MCLK | 16 | I | Master clock |
SCLK | 5 | I/O | Serial data bit clock |
LRCK | 6 | I/O | Serial data left and right channel frame clock |
SDOUT | 2 | O | Serial data output |
RESETb | 7 | I | Active low chip reset (low power) |
AINL, AINR | 8,10 | I | Analog left and right inputs |
VDDP | 1 | I | Power supply for the digital input and output |
VDDD/GNDD | 4,3 | I | Digital power supply |
VDDA/GNDA | 11,12 | I | Analog power supply |
REFP | 13 | O | Filtering capacitor connection |
REFQ | 9 | O | Filtering capacitor connection |
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